Nonvolatile memories, such as EEPROMs(electrically erasable and programmable memories), use an internally generated high voltage, and a power supply voltage, by which data bits are programmed into memory cells and erased from the memory cells. With the construction of the memory cell in which a floating gate is interposed and electrically isolated between a control gate and a channel region, charges for a data bit are charged at the floating gate to program the memory cell and discharged from the floating gate to perform an erase operation of the memory cell. To perform these functions, an EEPROM needs a voltage high enough to create an electric field between the floating gate and channel region (or bulk region), causing the charges for a data bit to be put into a tunneling condition therebetween. The high voltage generator in the EEPROM is generally referred to as a charge pump circuit. High voltages are generated from a main charge pump circuit and from a local charge pump circuit (or switch charge pump circuit) which receives an output voltage from the main charge pump circuit. High voltage generated by the local charge pump circuit is applied to word lines coupled to control gates of the memory cells (or cell transistors), as disclosed in U.S. Pat. No. 5,473,563.
The local charge pump circuit shown in FIG. 1 provides, during a program mode, a voltage of about 20 V to control gates of cell transistors coupled to a selected word line while unselected word lines are held at a pass voltage of about 10 V . FIG. 1, illustrates a local charge pump, having a generic configuration for the purpose of creating high voltage, including depletion-type MOS (metal-oxide-semiconductor) capacitor 102 and enhancement-typed NMOS field effect transistors 103, 104, 107 and 108. Clock pulse .phi.P generated from oscillator 101 is applied to one electrode of capacitor 102 and the other electrode of capacitor 102, node 110, is connected to the drain and gate of transistor 103. The gate of transistor 103 is coupled to a high voltage generator 105, e.g., the aforementioned main charge pump generating high voltage VH. At switching node 111 connected to the source of transistor 103, the gate of transistor 104 and the gate of transistor 108 which is connected between high voltage generator 105 and output terminal 109, input voltage Vin is loaded through transistor 107 whose gate is fixed to power supply voltage Vcc.
Clock pulse .phi.P, as shown in FIG. 2, has an amplitude between a ground voltage (0 V ) and, the power supply voltage Vcc. In order to provide a stable high voltage to a selected word line, first as a precharging step, input voltage Vin is equivalent to Vcc and is applied to input terminal 106, thereby the precharge voltage at node 111 is Vin-Vtn where Vtn is the threshold voltage of transistor 107. The output voltage Vout becomes Vin-2 V tn where 2 V tn is a sum of threshold voltages of transistors 107 and 108. The voltage at node 110 is also Vin-2 V tn during the precharge period. Thereafter, clock pulse .phi.P goes to Vcc and node 110 is pulled up to Vin-2 V tn+.DELTA.V (.DELTA.V denotes an incremented value of voltage) from the precharge level Vin-2 V tn due to a capacitive coupling by capacitor 102. Switching node 111 retains a voltage of Vin-2 V tn+.DELTA.V-VTN (VTN is threshold voltage of transistor 103), which is higher than the precharge level Vin-Vtn by .DELTA.V-Vtn-VTN. Consequently, while .phi.P is being pulled down to the ground voltage along its falling edge, the voltage level on node 110 is lowered to Vin-2 V tn from Vin-2 V tn+.DELTA.V, by .DELTA.V, by means of a decoupling capacitance through capacitor 102. Since the voltage level at node 110, Vin-2 V tn, is lower than the voltage level at switching node 111 Vin-2 V tn+.DELTA.V-VTN, the current voltage level of node 110 becomes Vin-3 V tn+.DELTA.V-VTN due to decreasing the threshold voltage of transistor 104. The voltage level that switching node 111 is Vin-3 V tn+2.DELTA.V-2 V TN. As a result, the voltage level of node 111 is increased by .DELTA.V-(Vtn+VTN) due to the charge accumulation resulting from every rising edge of clock pulse .phi.P generated from oscillator 101.
In order to secure a stabilized application of high voltage output to selected word lines from the charge pump circuit, the .DELTA.V may not be lower than the sum of threshold voltages of transistors 103 and 104, i.e., Vtn+VTN. However, in a low power memory the voltage .DELTA.V is not high enough to overcome Vtn+VTN. Further, it is impossible to boost the output voltage because a body effect induced by an increasing voltage level on node 111 causes the threshold voltages of transistors 103 and 104 to increase, and because the low power supply voltage limits the available charge accumulation on switching node 111. The body effect, otherwise referred to as substrate bias effect or back-bias effect, appears when the junction of the source of a transistor and a substrate is in a reverse-biased condition caused by increasing the threshold voltage of a transistor such as 103 or 104. A generic formula defining the threshold voltage (vt) involved in the body effect is as follows, EQU Vt=Vfb+.phi.f+.UPSILON.(2.phi.f+Vsb)
where Vfb is flat-band voltage, .phi.f is work function, .UPSILON. body coefficient and Vsb substrate bias sensitivity.
In the above equation, Vsb is inclined to be sensitive to a substrate voltage while voltage V110 at node 110 and voltage V111at switching node 111 are increasing by themselves, causing the threshold voltages of transistors 103 and 104 to be increased thereby. Therefore, increasing the threshold voltages of the switching transistors 103 and 104 in a low power supply voltage deteriorates the transconduction characteristic with high pumping voltage. Accordingly, the voltage .DELTA.V is not high enough to overcome the threshold voltages of transistors 103 and 104, i.e., .DELTA.V&gt;Vtn+VTN is not achieved (as aforementioned, Vtn and VTN are threshold voltages of transistors 104 and 103, respectively). For example, assuming that the power supply voltage Vcc is 3 V and the coupling ratio of capacitor 102 is 0.9, .DELTA.V and Vth+VTH become about 2.7 V and 1.8 V, respectively. Therefore, the output voltage Vout does not reach let alone exceed 18 V . Referring to FIG. 2, the output voltage Vout is increased during period T1 through which clock pulse .phi.P retains the level of Vcc. But, if Vout rises over 16 v, the increased V111 causes the body effect to be deeper and thereby the coupling voltage .DELTA.V is rapidly reduced to blunt stepping levels of the output voltage Vout. FIG. 4 shows a variation of the output voltage Vout when the power supply voltage Vcc is sloped down, by 0.2 V, to 2.4 V from 3.0 V, demonstrating that the reduction of the power supply voltage is directly involved in decreasing the output voltage Vout of the charge pump circuit.